BUILT IN SELF HEATING THERMAL TESTING OF FPGAs.
Author
ANJANA G
Last Updated
6 years ago
License
Creative Commons CC BY 4.0
Abstract
Presentation about build in self heating thermal testing of FPGAs.
Presentation about build in self heating thermal testing of FPGAs.
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\title[BIST]{BUILT IN SELF HEATING THERMAL TESTING OF FPGAs.} % The short title appears at the bottom of every slide, the full title is only on the title page
\author{ANJANA G.} % Your name
\institute[RIT KOTTAYAM.] % Your institution as it will appear on the bottom of every slide, may be shorthand to save space
{
AECE S1.
\textit{Roll No:4.} \\ % Your institution for the title page
\medskip
\textit{Guide:Mrs.JAYALAKSHMI S NAIR.}% Your email address
}
\date{\ 20/09/2016.} % Date, can be changed to a custom date
\begin{document}
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\titlepage % Print the title page as the first slide
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\begin{frame}
\frametitle{OUTLINE.} % Table of contents slide, comment this block out to remove it
\tableofcontents % Throughout your presentation, if you choose to use \section{} and \subsection{} commands, these will automatically be printed on this slide as an overview of your presentation
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% PRESENTATION SLIDES
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\section{INTRODUCTION.}
\section{EXISTING SYSTEM.}
\section{PROPOSED SYSTEM.}
\subsection{3.1 BLOCK DIAGRAM.}
\subsection{3.2 SELF HEATING CHAIN.}
\subsection{3.3 SHE INTEGRATION WITH BIST.}
\section{RESULTS.}
\subsection{4.1 SIMULATION RESULTS.}
\subsection{4.2 RTL SCHEMATICS.}
\subsection{4.3 DEVICE UTILISATION SUMMARY.}
\section{ADVANTAGES.}
\section{DISADVANTAGES.}
\section{FUTURE SCOPE.}
\section{COCLUSION.}
\section{REFERENCES.}
\begin{frame}
\frametitle{1.INTRODUCTION.}
\begin{itemize}
\item A Built – In Self Test or Built – In Test is a mechanism that Permits a machine to test itself.
\item A thermal-aware testing of FPGAs using built-in self-heating.
\item The internal logic resources of FPGA are used to build controlled self-heating elements (SHEs).
\item Controlled SHE's are integrated with the test schemes.
\item Two categories of SHE integration are there, they are
\textit{1.BIST in application independent testing.}
\textit{2.self heating application dependent testing.}
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{2. EXISTING SYSTEM.}
\begin{block}{2.1. BURN IN TESTING.}
\begin{itemize}
\item The chip is exposed to high temperatures and/or voltages for certain periods.
\item Accelerate the aging and stress of the chip before applying the test.
\item External devices are used for heating up the chip.
\end{itemize}
\end{block}
\begin{block}{2.2.THERMAL AWARE METHODS.}
\begin{itemize}
\item The chip is first heated to a certain temperature and then the test is applied.
\item External devices such as thermal chambers and ovens are used for the purpose of heating up the chip.
\end{itemize}
\end{block}
\end{frame}
%------------------------------------------------
\begin{frame}
\frametitle{3.PROPOSED SYSTEM.}
\begin{itemize}
\item Utilizing the idea of self heating.
\item Make the FPGA able to generate heat by increasing the power consumption.
\textbf{3.1.BLOCK DIAGRAM.}
\item The basic block diagram of the BIST is depicted in figure 3.1.1.
\item Consist of -
\textit{1.Test pattern generator.}
\textit{2.Block under test.}
\textit{3.Output response analyzer.}
\textit{4.Test controller.}
\end{itemize}
\end{frame}
\begin{frame}
\begin{center}
\begin{figure}
\textit{BLOCK DIAGRAM}
\includegraphics[width=11cm]{1.eps}
\textit{fig:3.1.1.BIST}
\end{figure}
\end{center}
\end{frame}
\begin{frame}
\textit{BIST consists of several blocks as shown above.}
\begin{itemize}
\item a) Test pattern Generator(TPG) : This is a circuit to be tested, a way to compress those results and way to analyze them.
\textit{-It generates the test patterns for CUT. Here a Linear feedback shift register is used to generate patterns.}
\textit{-Patterns are generated in pseudo random fashion.}
\item b) Circuit under test(CUT) : The portion of the circuit tested in BIST mode. It can be combinational, sequential or a memory.
\item c) Output Response Analyzer: It acts as a comparator with stored responses.
\textit{-Compares the test output with the stored response and shows whether the chip passes or fails the test.}
\item d) Test controller: It controls the test execution.
\textit{- It provides the control signal to activate all blocks.}
\textit{- If control signal is 0,then BIST is said to be in test mode and if 1,in normal mode.}
\end{itemize}
\end{frame}
\begin{frame}
\textbf{3.2.SELF HEATING CHAIN.}
\begin{itemize}
\item SHC controls the heat generated in the FPGA.
\item Consist of a number of self heating elements.
\item A Self heating element is depicted in figure 3.2.1.
\item Consist of control circuit and toggle LUT'S.
\begin{figure}
\includegraphics[width=11cm]{2.eps}
\textit{fig:3.2.1.SHE}
\end{figure}
\end{itemize}
\end{frame}
\begin{frame}
\begin{itemize}
\item Basic toggle logic is depicted in figure 3.2.2.
\item The circuit can be realized using an LUT with at least two inputs.
\item The feedback signal from the LUT output to its input goes through switching resources.
\item Causes the resources to toggle as well and hence their dynamic power consumption will increase.
\item Thus enabling more heat to be generated.
\item The Toggle LUT circuit is depicted in figure 3.2.3.
\item To maximize the power consumption, each of the proposed SHEs consists of several toggling LUTs.
\end{itemize}
\end{frame}
\begin{frame}
\begin{figure}
\includegraphics[width=8cm]{3.eps}
\textit{fig:3.2.2.BASIC TOGGLE}
\end{figure}
\begin{figure}
\includegraphics[width=8cm]{4.eps}
\textit{fig:3.2.3.TOGGLE LUT}
\end{figure}
\end{frame}
\begin{frame}
\begin{itemize}
\item The control circuit sends serial out signal to the control input ports of toggling LUT'S.
\item The control circuit of SHE is depicted in figure 3.2.4.
\item Consist of flip flop working as a shift register.
\end{itemize}
\begin{figure}
\includegraphics[width=11cm]{5.eps}
\textit{fig:3.2.4.CONTROL CIRCUIT}
\end{figure}
\end{frame}
\begin{frame}
\begin{itemize}
\item In a single SHE, all of the toggling LUTs can be either in toggling mode or stopped, all at the same time.
\item If SHE contains too many LUTs, a fine control of the generated temperature cannot be achieved.
\item The serial-in and serial-out ports of multiple SHE's are connected together.
\item Thus a SHE chain is developed.
\item The SHE chain is depicted in the figure 3.2.5.
\item Consist of a heating control input,clock and reset.
\end{itemize}
\end{frame}
\begin{frame}
\begin{figure}
\includegraphics[width=11cm]{6.eps}
\textit{fig:3.2.5.SHE CHAIN}
\end{figure}
\end{frame}
\begin{frame}
\textbf{3.3.SHE INTEGRATION WITH BIST.}
\textit{Two methods of integration of self heating with BIST are-}
\begin{itemize}
\item Sequential methods.
\textit{-FPGA's are loaded with SHE for heating up the chip in multiple heat and test configuration.}
\textit{-no need to modify original BIST structure.}
\item Concurrent methods.
\textit{-FPGA's are loaded with SHE for heating up the chip in single heat and test configuration.}
\textit{-Original BIST structure is modified in order to free up enough logic resources for SHE.}
\textit{-Most commonly adopted technique.}
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{4.RESULTS.}
\textbf{4.1. SIMULATION RESULTS.}
\begin{figure}
\includegraphics[width=11cm]{7.eps}
\textit{fig:4.1.1.BASIC TOGGLE SIMULATION}
\end{figure}
\end{frame}
\begin{frame}
\begin{figure}
\includegraphics[width=11cm]{10.eps}
\textit{fig:4.1.2.TOGGLE LUT SIMULATION}
\end{figure}
\end{frame}
\begin{frame}
\begin{figure}
\includegraphics[width=11cm]{13.eps}
\textit{fig:4.1.1.SHE SIMULATION}
\end{figure}
\end{frame}
\begin{frame}
\textbf{4.2.RTL SCHEMATIC.}
\begin{figure}
\includegraphics[width=11cm]{9.eps}
\textit{fig:4.2.1.BASIC TOGGLE RTL}
\end{figure}
\end{frame}
\begin{frame}
\begin{figure}
\includegraphics[width=11cm]{12.eps}
\textit{fig:4.2.2.TOGGLE LUT RTL}
\end{figure}
\end{frame}
\begin{frame}
\begin{figure}
\includegraphics[width=11cm]{14.eps}
\textit{fig:4.2.3.SHE RTL}
\end{figure}
\end{frame}
\begin{frame}
\begin{figure}
\includegraphics[width=11cm]{16.eps}
\textit{fig:4.2.4.SHE CHAIN RTL}
\end{figure}
\end{frame}
\begin{frame}
\textbf{4.3.DEVICE UTILIZATION SUMMARY.}
\begin{tabular}{|c|c|c|c|c|}
\hline
- & Basictoggle & ToggleLUT & Controlckt & SHE \\
\hline
No: of LUT’S & 1/63400 & 1/63400 & 1/63400 & 1/63400\\
\hline
LUT Flip flop pairs & 1 & 1 & 1 & 1 \\
\hline
Number of I/o & 3 & 5 & 5 & 8 \\
\hline
delay &0.753ns & 0.834ns & 0.834ns & 0.983ns \\
\hline
\end{tabular}
\end{frame}
\begin{frame}
\frametitle{5.ADVANTAGES.}
\begin{itemize}
\item Eliminates the need of any external device.
\item Reducing the test cost and test time.
\item Assuring heating only the FPGA chip and not any other component on the board.
\item Generate uniform temperature on the chip.
\item No limitation on the number of FPGA chips to be heated in parallel.
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{6.DISADVANTAGES.}
\begin{itemize}
\item Performance penalty due to larger signal routing path in BIST.
\item Area overheads.
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{7.FUTURE SCOPE.}
\begin{itemize}
\item Utilized for real time applications such as FPGA implementation of BIST enabled UART.
\item A restartable BIST controller for fault detection of FPGA can be possible.
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{8.CONCLUSION.}
\begin{itemize}
\item Increasing chip temperature is one of the most important challenges that face chips at nano-scale.
\item various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing to detect them.
\item Thus a self heating approach for thermal-aware testing of FPGA devices is implemented.
\item Upon simulation high accuracy is achieved.
\end{itemize}
\end{frame}
\begin{frame}
\frametitle{9.REFERENCES.}
\textit{[1] A. Amouri, J. Hepp, and M. Tahoori, “Built In Self Heating Thermal Testing Of FPGAs,” in Proc. IEEE transactions on CAD of integrated circuits and systems,VOL. 35, NO. 9, September 2016.}
\textit{[2] A. Amouri, J. Hepp, and M. Tahoori, “Self-heating thermal-aware testing of FPGAs,” in Proc. IEEE 32nd VLSI Test Symp. (VTS), Napa, CA, USA, Apr. 2014, pp. 1–6.}
\textit{[3] C. Liu, K. Veeraraghavan, and V. Iyengar, “Thermal-aware test scheduling and hot spot temperature minimization for core-based systems,” in Proc. 20th IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. (DFT), Monterey, CA, USA, 2005, pp. 552–560.}
\textit{[4] B. F. Dutton and C. E. Stroud, “Built-in self-test of configurable logic blocks in Virtex-5 FPGAs,” in Proc. 41st Southeastern Symp. Syst. Theory (SSST), Tullahoma, TN, USA, 2009, pp. 230–234.}
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\Huge{\centerline{The End}}
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