Rishabh Jain's CV.
Resume sample for VLSI engineers. Created using the AltaCV template.
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% This is an example CV created using altacv.cls (v1.1.5, 1 December 2018) written by
% LianTze Lim (liantze@gmail.com), based on the
% Cv created by BusinessInsider at http://www.businessinsider.my/a-sample-resume-for-marissa-mayer-2016-7/?r=US&IR=T
%
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\begin{document}
\name{Rishabh Jain}
\tagline{VLSI Engineer}
% Cropped to square from https://en.wikipedia.org/wiki/Marissa_Mayer#/media/File:Marissa_Mayer_May_2014_(cropped).jpg, CC-BY 2.0
%\photo{3.3cm}{profile.jpg}
\personalinfo{%
% Not all of these are required!
% You can add your own with \printinfo{symbol}{detail}
\email{rishabhjain7b@gmail.com}
\phone{+919810203807}
% \mailaddress{Address, Street, 00000 County}
\location{New Delhi, India}
% \homepage{marissamayr.tumblr.com/}
% \twitter{@marissamayer}
\linkedin{linkedin.com/in/rishabh-jain-1605b6116/}
\github{github.com/rishabhjain7b} % I'm just making this up though.
% \orcid{orcid.org/0000-0000-0000-0000} % Obviously making this up too. If you want to use this field (and also other academicons symbols), add "academicons" option to \documentclass{altacv}
}
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\makecvheader
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\cvsection[page1sidebar]{Experience}
\cvevent{SOFTWARE ENGINEER (Contractual Employee)}{Xilinx Inc.}{June 2018 -- Present}{Hyderabad, India}
\begin{itemize}
\item Designing C++/OpenCL based kernels for FPGA and Handling SDx Examples for SDAccel and SDSoC Environment.
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\end{itemize}
\divider
\cvevent{ASSISTANT TRAINER FOR HEP}{Mentor Graphics Pvt. Ltd.}{May 2018 -- June 2018}{Noida, India}
\begin{itemize}
\item Instructing Undergraduate students in the Professional Training for Verification of Electronic Designs using System Verilog.
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\end{itemize}
\divider
\cvevent{DESIGN AND VERIFICATION ENGINEER TRAINEE}{DKOP Labs Pvt. Ltd.}{January 2018 -- May 2018}{Noida, India}
\begin{itemize}
\item Industry—based training and hands—on experience of Front End VLSI domain using tcl/shell, Verilog and System Verilog.
%\smallskip
\end{itemize}
\divider
\cvevent{HEP TRAINEE (DESIGN AND VERIFICATION ENGINEER)}{Mentor Graphics Pvt. Ltd.}{June 2018 -- July 2018}{Bangalore, India}
\begin{itemize}
\item Selected amongst top 30 students across India.
\item Verification of Electronic Designs (designed in Verilog) using Layered, Object Oriented Test benches in System Verilog.
%\smallskip
\end{itemize}
\divider
\cvevent{EMBEDDED SYSTEM ENGINEER}{Gravity Innovations LLP}{2018 March -- December}{Delhi, India}
\begin{itemize}
\item Working on machines and electronic circuits based on Embedded Micro-controllers using Robotics and Internet of Things.
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\end{itemize}
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\cvsection{TECHNICAL SKILLS}
\cvskill{C/C++, Digital System Design}{4}
\cvskill{OpenCL, Makefile, Shell Scripting}{2}
\cvskill{Verilog/System Verilog, Python}{3}
%\divider
\cvsection{SOFTWARE SKILLS}
\begin{itemize}
\item QuestaSim Prime
\item Xilinx SDx, Vivado, ISE
\item Linux OS (Fedora/Ubuntu/CentOS)
\item Tanner Tool, PSpice
\item Proteus Pro ISIS
%\smallskip
\end{itemize}
% \cvevent{Product Engineer}{Google}{23 June 1999 -- 2001}{Palo Alto, CA}
% \begin{itemize}
% \item Joined the company as employe \#20 and female employee \#1
% \item Developed targeted advertisement in order to use user's search queries and show them related ads
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%\cvsection{A Day of My Life}
% Adapted from @Jake's answer from http://tex.stackexchange.com/a/82729/226
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% 10/10em/accent!30/Sleeping \& dreaming about work,
% 25/9em/accent!60/Public resolving issues with Yahoo!\ investors,
% 5/13em/accent!10/\footnotesize\\[1ex]New York \& San Francisco Ballet Jawbone board member,
% 20/15em/accent!40/Spending time with family,
% 5/8em/accent!20/\footnotesize Business development for Yahoo!\ after the Verizon acquisition,
% 30/9em/accent/Showing Yahoo!\ employees that their work has meaning,
% 5/8em/accent!20/Baking cupcakes
% }
\clearpage
% \cvsection[page2sidebar]{Publications}
\nocite{*}
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% \printbibliography[heading=pubtype,title={\printinfo{\faFileTextO}{Journal Articles}}, type=article]
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% \printbibliography[heading=pubtype,title={\printinfo{\faGroup}{Conference Proceedings}},type=inproceedings]
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